Electronic components, such as silicon integrated circuit chips or other electronic components, are subject to early failure during their life cycle. It is desirable to detect and eliminate the chips that are most prone to early failure prior to sending them to market. Additionally, it is desirable to identify the components of the chips that cause the early failures so that they may be improved. Thus, producers of these electronic components have found it cost-effective to utilize burn-in systems to rigorously temperature stress the integrated circuit chips while simultaneously powering them in order to detect under-performing chips.
Burn-in systems typically utilize burn-in boards to support a number of electronic components to be tested inside a burn-in oven. An exemplary burn-in oven 100, shown in FIG. 1, is typically configured to hold several racks of burn-in boards 102. Each burn-in board 102 typically includes multiple sockets 104 for holding integrated circuit chips or electronic devices 106 (hereinafter “chips”) that are to be stress tested, as illustrated in the schematic diagram of a burn-in system provided in FIG. 2.
The chips 106 on the burn-in board 102 are powered and exposed to heat stress over an extended period of time. During burn-in temperature stressing of the chips, heat exchange systems 108 are employed to maintain the chips within a desired temperature range to prevent overheating of the chips, which can damage properly functioning chips.
Burn-in systems also include one or more power stages 110 that are used to supply a desired power 111 to a testing stage 112 of the burn-in board 102, as illustrated in FIG. 2. The testing stage 112 handles the application of the power 111 supplied from the power stage 110 to the integrated circuit chips 106 being tested. Multiple power stages can be used to simultaneously supply power to the testing stage when the amount of power supplied by a single power stage is insufficient.
An exemplary power stage 110 in accordance with the prior art is illustrated schematically in FIG. 3. The power stage 110 includes one or more power supplies 116 that provide bulk power 118 for the power stage 110. A pulse width modulator (PWM) 120 modulates the bulk power 118 in response to a control signal 122 from a pulse width modulator controller 124 to control the power that is supplied to the testing stage 112.
It is important to control the voltage across the chips 106 or the electrical testing “load” 126 of the testing stage 112, during stress testing to ensure that the specifications of the test being conducted are met. For example, if the voltage across the testing load 126 is not in accordance with the specifications of the test, the testing results will be unreliable. Unfortunately, the task of maintaining the voltage across the load 126 at a desired level is made difficult by the fact that the load 126 will vary due to temperature changes in the chips and other factors over the course of a stress test.
Voltage control circuits, such as voltage control circuit 130 shown in FIG. 3, have been used to ensure that the desired voltage, or target load voltage 132, is applied across the load 126 of the testing stage 112 during chip stress testing. The voltage control circuit 130 generally operates by measuring the voltage across the load 126 of the testing stage 112 and comparing that measured load voltage 134 to the target load voltage 132. The difference between the measured load voltage 134 and the target load voltage 132 indicates an error, which is fed from the voltage control circuit 130 to the pulse width modulator controller 124 as a voltage error signal 136. The pulse width modulator controller 124 generates the control signal 122, based on the voltage error signal 136, that controls the pulse width modulator 120 to adjust the power 111 supplied to the power stage 112 as needed to change the measured load voltage 134 to the target load voltage 132. In this manner the voltage across the testing load 126 is maintained at the desired level.
The stress testing of high performance integrated circuit chips typically requires the application of high power to the resultant load 126 of the testing stage 112. This high power demand places a heavy demand on the power supply 116 of the power stage 110. In particular, as the load 126 of the testing stage 112 increases, the current supplied to the testing stage 112 from the power stage 110 must increase in order to maintain the desired target load voltage 132 across the testing load 126. Occasionally, the demand for current exceeds the capability of the power supply 116. In order to avoid damaging the power supply 116, various protection methods have been employed.
One protection method incorporated by prior art burn-in systems shuts down the pulse width modulator controller 124 and thus the pulse width modulators 120 when a current limit of the measured load current 142 is exceeded. Unfortunately, this protection method results in undesired interruptions to the stress testing of the chips.
In an effort to avoid interrupting ongoing chip stress testing, power protection has been provided to power stages 110 using a current control circuit 140 (FIG. 3) that operates discretely from the voltage control circuit 130 described above to prevent the current output from the power stage 110 to the testing stage 112 from exceeding preset current limits. The current control circuit 140 operates in a manner that is similar to the voltage control circuit 130 by measuring the current fed to the load 126 of the testing stage 112 with a current shunt 141, comparing this measured load current 142 to a target load current 144 and outputting a current error signal 146 that is related to the difference between the measured load current 142 and the target load current 144. The current error signal 146 produced by the current control circuit 140 is coupled to the voltage error signal 136.
When the power stage 110 provides a current to the testing stage that is less than the target load current 144, the power stage 110 operates in a “voltage control” mode, in which the control signal 122 to the pulse width modulator 120 is substantially independent of the current error signal 146 and substantially dependent on the voltage error signal 136. In other words, the control signal 122 received by the pulse width modulator 120 is substantially based on the difference between the measured load voltage 134 and the target load voltage 132.
However, when the power stage 110 provides a current (i.e., measured load current 142) to the testing stage 112 that exceeds the target load current 144, the power stage 110 switches from the voltage control mode to a “current control” mode, in which the control signal 122 received by the pulse width modulator 120 is substantially independent of the voltage error signal 136 and substantially dependent on the current error signal 146. In other words, the control signal 122 received by the pulse width modulator 120 is substantially based on the difference between the measured load current 142 and the target load current 144. While in the current control mode, the current output from the power stage 110 is reduced to a value that is equal to the target load current 144 regardless of the target and measured load voltages 132 and 134.
One problem with the arrangement depicted in FIG. 3 is that the switching between the voltage control mode and the current control mode produces a transient error in the signal to the pulse width modulator controller 124 for a period of time before it settles to a stable and useable signal. As a result, there is a delay in the switching between the voltage and current control modes. This delay limits the high power testing capability of the burn-in board 102 because the target or maximum load current level 144 must be reduced in order to ensure that the current limit of the power stage 110 is not exceeded.
Additionally, the modulated power output 111 produced by the power stage 110 typically comprises an errant voltage during transitions between the voltage and current control modes, which can affect the accuracy of the testing.
As mentioned above, multiple power stages 110 (FIG. 2) can be used to simultaneously supply power to the testing stage 112 when the amount of power supplied by a single power stage is insufficient. In general, the power outputs of one or more of the power stages 110 are coupled together to increase the power supplied to the testing stage 112, as illustrated by the dashed lines in FIG. 2. When the burn-in system is operating in such a multiple power mode, it is desirable to control the power supplied by the power stages 110 using a single set of voltage and current control circuits.
Unfortunately, the voltage and current control circuits used to control a single power stage (i.e., single power mode) are different from the voltage and current control circuits that are required to control a combination of two power stages (i.e., dual power mode) where the power outputs of two power stages 110 are combined. In general, each different power mode of the burn-in system (i.e., single, dual, triple, quad, etc.) requires different voltage and current control circuits.
There is a continuous demand for improvements to burn-in systems including, for example, more seamless switching between current and voltage control modes of the power stage and easier setup of the burn-in system power mode.
Embodiments of the present invention provide solutions to these and other problems, and offer other advantages.